This relates to integrated circuits and more particularly, to circuitry for detecting soft errors in integrated circuits with memory elements.
Integrated circuits often include memory elements that are based on random-access memory (RAM) cells. For example, integrated circuits often include memory elements such as static random-access memory (SRAM) cells, configuration random-access memory (CRAM) cells (e.g., cells that are loaded with configuration data to provide static 10 output signals to programmable circuitry), etc.
During normal operation, an integrated circuit may be subject to environmental background radiation. Particularly in modern devices that contain large numbers of memory cells, there is a possibility that a radiation strike on a memory cell will cause the memory cell and its neighboring cells to change their states (e.g., a radiation strike may induce multi-bit upsets).
Radiation-induced errors that arise in random-access memory cells are sometimes referred to as soft errors. Soft errors are undesirable, because they can potentially cause device malfunction. One way in which soft errors can be addressed is to change the design of the configuration random-access memory cells. However, changes to the configuration random-access memory cells can introduce undesired circuit complexity and can consume additional circuit real estate.
As the density of memory circuitry on integrated circuits increases, multi-bit upsets in adjacent cells become more frequent. In an effort to counteract multi-bit upsets, error correcting coding (ECC) techniques have been developed. Error detection circuitry implemented using convention error correcting codes are capable of detecting and correcting single-bit errors, detecting double-bit errors, and detecting and correcting adjacent double-bit errors. This type of error correcting code is referred to as a single-error-correcting, double-error-detecting, double-adjacent-error-correcting (SEC-DED-DAEC) code.
The conventional SEC-DED-DAEC code, however, is not capable of detecting triple-bit errors. As a result, other codes have been developed that are capable of detecting and correcting all double-bit errors and detecting all triple-bit errors. A double-error-correcting, triple-error-detecting (DEC-TED) code of this type may be used at the cost of significant overhead.
It would therefore be desirable to be able to provide improved error detection circuitry.